Method of forming uniformly planarized structure in a semiconductor wafer
US6689697B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2000 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Jan 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76837
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a uniformly planarized structured in a semiconductor wafer forms metal structures on a substrate layer with spaces between the structures. The top surfaces of the metal structures lie within a common plane. Dielectric material is deposited on the layer, the metal structures and in the spaces. The dielectric layer is first etched so that the dielectric material in the spaces is below the common plane. Additional dielectric material is then deposited on the layer, the metal structures and in the spaces. The dielectric layer is then subjected to a second etching. Further deposition and etching steps are performed until the top of the dielectric layer and the top surfaces of the metal structures have a common, substantially uniform planarization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.