Devices containing platinum-rhodium layers and methods
US6690055B1 · kind B1 · utility
20Cited by
55References
20Claims
0Family size
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Key dates
| Filing date | Aug 30, 2000 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Mar 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.