Function block architecture for gate array
US6690194B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1999 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Oct 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.