Multi-bit PROM memory cell
US6690597B1 · kind B1 · utility
32Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2003 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Apr 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell comprises at least two antifuses in series with a diode. Each antifuse expresses a different resistance from the others when blown, and each requires an escalating programming voltage over the last to be programmed. The antifuse structures differ in their respective geometries and materials so that a low programming voltage will blow the more sensitive fuse first, and a higher voltages will program the lesser sensitive fuses thereafter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.