Method and circuit for adjusting the timing of output data based on an operational mode of output drivers
US6693472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2002 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Sep 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.