Double data rate scheme for data output
US6694416B1 · kind B1 · utility
10Cited by
32References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1999 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Sep 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, devices, and methods. A double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.