Method for formation of a differential offset spacer

US6696334B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Kay Hellig · Austin, US
• Srikanteswara Dakshina-Murthy · Wappingers Falls, US
• Christoph Schwan · Gebhardshain, DE

Key dates

• Filing date: Sep 30, 2002
• Grant date: Feb 24, 2004
• Expiry date: Sep 30, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0184

Abstract

A method for differential offset spacer formation suitable for incorporation into manufacturing processes for advanced CMOS-technologies devices is presented. The method comprises forming a first insulative layer overlying a plurality of gate structures, then forming a second insulative layer overlying the first insulative layer. A mask is formed to expose a first portion of the second insulative layer overlying a gate structure of a first transistor type, and to protect a second portion of the second insulative layer overlying a gate structure of a transistor of a second transistor type. The exposed first portion of the second insulative layer overlying the gate structure of the first type is then etched. After etching, the mask is removed, and the exposed second portion of the second insulative layer and the first insulative layer are etched to form differential spacers abutting the gate structures. Endpoint is utilized to halt the spacer etch process.