Method of fabricating memory device

US6696350B2 · kind B2 · utility

Assignee

• POWERCHIP SEMICONDUCTOR CORP. · TW

Inventors

• Chih-Wei Hung · Baoshan, TW
• Da Sung · Hsinchu, TW
• Chien-Chih Du · Hsinchu, TW

Key dates

• Filing date: Jun 13, 2002
• Grant date: Feb 24, 2004
• Expiry date: Jun 13, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A method of fabricating a memory device. A plurality of isolation structures and a plurality of stacked gate structures are sequentially formed on a substrate. While defining the stacked gate structures, the isolation structures are over etched to form a plurality of trenches. A material layer is filled into the trenches. A patterned photoresist layer is formed on the substrate, while a part of the substrate predetermined for forming a drain region is exposed. An ion implantation step is performed to implant a dopant into the part of substrate predetermined for forming the drain region, such that a well is formed. As the trenches are filled with the material layer, the dopant cannot penetrate therethrough.