Memory cell with vertical transistor and trench capacitor
US6696717B2 · kind B2 · utility
9Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2002 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Nov 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
A memory cell with a vertical transistor and a trench capacitor. The memory cell includes a substrate having a trench and a trench capacitor disposed in the lower trench. A control gate, with a p-type polysilicon germanium layer and an overlying p-type polysilicon layer, is disposed in the upper trench and insulated from the substrate. A first insulating layer is disposed between the trench capacitor and the control gate. A first doped region is formed in the substrate around the first insulating layer and a second doped region is formed in the substrate around the second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.