Vertical MOSFET with ultra-low resistance and low gate charge
US6696726B1 · kind B1 · utility
32Cited by
15References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 16, 2000 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Aug 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.