Delay locked loop compensating for effective loads of off-chip drivers and methods for locking a delay loop
US6696872B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2002 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Sep 23, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop (DLL) for use in a semiconductor device includes a phase detector that receives a reference clock signal and a feedback clock signal and provides a delay control signal to a latch. The latch provides a latched delay control signal to a delay circuit. The delay circuit receives the reference clock signal in addition to the latched delay control signal, and provides a delayed clock signal. An off chip driver (OCD) receives the delayed clock signal and provides an interim feedback clock signal to a receiver. The receiver provides the feedback clock signal to the phase detector, thus completing the loop. The DLL may also include a means for receiving and responding to an update command, wherein the update command causes loop to open, and the latch to store the delay control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.