Method and apparatus for analyzing line structures
US6697153B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2002 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Mar 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N2021/95615
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and an apparatus for analyzing line structures during semiconductor wafer processing. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Film property data from the semiconductor wafer is acquired. Data from a reference library is accessed; the data comprising optical data relating to a line structure formation on a semiconductor wafer, based upon the film property data. The metrology data is compared to data from the reference library. A line structure fault detection analysis is performed in response to the comparison of the metrology data and the reference library data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.