Method for balanced-delay clock tree insertion
US6698006B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2001 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | May 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock tree insertion method for distributing a clock signal in an integrated circuit design includes providing a physical design representative of the integrated circuit design, specifying a location for a root node of the clock tree in the physical design, constructing an array of buffers as the clock tree where the array of buffers is constructed to minimize the maximum insertion delay from the root node to the clock signal endpoints and to meet a predefined maximum insertion delay constraint, identifying locations in the clock tree where clock skew violations occur and correcting the clock skew violations by introducing delay at buffer locations in the clock tree having the fastest clock signal arrival times, and identifying locations in the clock tree where minimum insertion delay violations occur and correcting the minimum insertion delay violations by slowing down the arrival times of clock signal endpoints of the clock tree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.