Methods of fabricating integrated circuit devices with contact hole alignment
US6699762B2 · kind B2 · utility
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23References
8Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 12, 2002 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Jun 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and an insulating region, a contact pad on the conductive region of the semiconductor substrate, an auxiliary pad adjacent to the contact pad, and an interlevel insulating layer on the semiconductor substrate and having a contact hole for exposing both the contact pad and the auxiliary pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.