Gate etch process
US6699795B1 · kind B1 · utility
4Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2002 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Mar 15, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/952
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.