Circuit optimization for minimum path timing violations
US6701505B1 · kind B1 · utility
29Cited by
6References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2001 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Feb 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided to optimize delay insertions for reducing timing violations. The method includes inserting a buffer between a driver and a receiver in a timing path and placing the buffer either inside or outside a bounding box that encloses the driver and the receiver. The placement of the buffer inside or outside the bounding box creates the appropriate effective loading on the buffer to generates the required minimum delay to avoid timing violations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.