Method for match delay buffer insertion
US6701506B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2001 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | May 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1506
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for “match-delay” buffer insertion is provided to add delays at a node without changing the input capacitance of the node as seen by the upstream node. In one embodiment, a method for inserting a delay in a node in an electrical design associated with a logic gate includes: adding the delay at the node by adding a new logic gate before the node where the new logic gate is the same cell type as the logic gate and is positioned near the logic gate. The method may further include: determining if the delay can be added by adding a new logic gate before the node, and if a new logic gate cannot be added before the node, adding the delay by adding a new logic gate after the logic gate where a combination of the logic gate and the new logic gate giving the delay to be added.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.