Alignment processing mechanism and semiconductor processing device using it
US6702865B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2000 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Oct 4, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/141
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alignment processing mechanism 10 according to the present invention includes: a conveying mechanism 11 for conveying a substrate W to be processed, an alignment mechanism 12 for aligning the substrate W conveyed by the conveying mechanism 11 to a predetermined direction, and a buffer mechanism 13 for relaying the substrate W from the conveying mechanism 11 to the alignment mechanism 12. The buffer mechanism 13 is adapted to temporarily hold the substrate W conveyed by the conveying mechanism 11, and to pass the temporarily holding substrate W to the alignment mechanism 12 based on a state of the alignment mechanism 12. According to the present invention, the alignment mechanism 12 can be used with greater efficiency in order to achieve a high speed of an alignment process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.