Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange
US6704843B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2000 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Mar 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System bus snoopers within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the dynamic application sequence behavior information for the target cache line to their snoop responses. The system controller, which may also maintain dynamic application sequence behavior information in a history directory, employs the available dynamic application sequence behavior information to append “hints” to the combined response, appends the concatenated dynamic application sequence behavior information to the combined response, or both. Either the hints or the dynamic application sequence behavior information may be employed by the bus master and other snoopers in cache management.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.