Apparatus and method for improved precomputation to minimize power dissipation of integrated circuits
US6704878B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1996 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Sep 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an IC chip, a novel precomputation architecture and process which grants improved reductions in power dissipation, requires less logic to implement, and relaxes critical timing constraints. A first computation circuit is used to calculate output values if precomputation cannot be performed. However, if the output values can be precomputed, a second circuit is used to calculate the output values. The second computation circuit is smaller, simpler, and consumes less power than the first computation circuit. An extremely small and simple decision circuit, which dissipates a minimal amount of power, is used to determine whether precomputation is possible. This determination is made at a previous cycle, whereas the actual computation of the output cycles are postponed to be performed in a subsequent cycle. Depending on whether precomputation can be performed, either the first computation circuit or the second computation circuit is activated while the unused computation circuit is disabled in order to conserve power. The decision circuit also directs a multiplexer to select output values generated by either the first computation circuit or the second computation circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.