Control of separation between transfer gate and storage node in vertical DRAM
US6706634B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2000 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Feb 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0383
Abstract
A high density plasma deposition process for eliminating or reducing a zipper-like profile of opened-up voids in a poly trench fill by controlling separation between a transfer gate and storage node in a vertical DRAM, comprising:etching a recess or trench into poly Si of a semiconductor chip;forming a pattern of SiN liner using a mask transfer process for formation of a single sided strap design;removing the SiN liner and etching adjacent collar oxide away from a top part of the trench;depositing a high density plasma (HDP) polysilicon layer in the trench by flowing either SiH4 or SiH4+H2 in an inert ambient;employing a photoresist in the trench and removing the high density plasma polysilicon layer from a top surface of the semiconductor to avoid shorting in the gate conductor either by spinning on resist and subsequent chemical mechanical polishing or chemical mechanical downstream etchback of the polysilicon layer; andstripping the photoresist and depositing a top trench oxide by high density plasma.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.