Method of forming integrated circuitry, method of forming a capacitor, method of forming DRAM integrated circuitry and DRAM integrated category

US6707088B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventor

• Fred Fishburn · Boise, US

Key dates

• Filing date: Jul 31, 2002
• Grant date: Mar 16, 2004
• Expiry date: Aug 3, 2022

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/908

Abstract

In one implementation, integrated circuitry includes a first capacitor electrode layer received over a substrate. A capacitor dielectric layer is received over the first capacitor electrode layer. The capacitor dielectric layer has an edge terminus. A second capacitor electrode layer is received over the capacitor dielectric layer. The first capacitor electrode layer and the second capacitor electrode layer, respectively, have opposing lateral edges. The capacitor dielectric layer edge terminus is laterally coincident with at least a portion of one of the opposing lateral edges of the second capacitor electrode layer. An insulative silicon nitride including cap is received over the capacitor dielectric layer edge terminus and the one opposing lateral edge of the second capacitor electrode layer. The cap does not contact any portion of the opposing lateral edges of the first capacitor electrode layer. Other aspects and implementations are disclosed.