Semiconductor memory device
US6707736B2 · kind B2 · utility
5Cited by
7References
18Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 10, 2002 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Jun 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, a plurality of input/output terminals to input cell data written to the memory cell array and output cell data read from the memory cell array, a test mode setting circuit which sets a test mode to monitor a plurality of timing signals which control input/output operation timing of the cell data, and switch circuits connected to the plurality of input/output terminals. The switch circuits simultaneously output the plurality of timing signals from the plurality of input/output terminals in the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.