Memory system with channel multiplexing of multiple memory devices
US6708248B1 · kind B1 · utility
56Cited by
15References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1999 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Dec 8, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.