Source/drain extension fabrication process with direct implantation
US6709938B2 · kind B2 · utility
3Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jul 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved source/drain extension process is provided by the following processing steps of implanting NMOS devices directly on either side of the gates without an oxide layer (step D2), covering the gates with a cap oxide layer(step E2), covering NMOS devices with photoresist(step F2), dry etching all PMOS devices (Step G2), and implanting PMOS devices (step I2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.