Double spacer FinFET formation
US6709982B1 · kind B1 · utility
174Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Nov 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.