Patent · US Expired

Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the ferroelectric transistor

US6710388B2 · kind B2 · utility

1Cited by

12References

16Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Haneder · Hersbruck, DE
Hans Reisinger · Grünwald, DE
Reinhard Stengl · Stadtbergen, DE
Harald Bachhofer · Hersbruck, DE
Hermann Wendt · Grasbrunn, DE
Wolfgang Hönlein · Unterhaching, DE

Key dates

Filing date	Mar 7, 2001
Grant date	Mar 23, 2004
Priority date	—
Expiry date	Apr 25, 2021

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/701
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.