Three-dimensional memory cache system
US6711043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jun 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The preferred embodiments described herein provide a three-dimensional memory cache system. In one preferred embodiment, a modular memory device removably connectable to a host device is provided. The modular memory device comprises a substrate, a cache memory array, a three-dimensional primary memory array, and a modular housing. The cache memory array and the three-dimensional primary memory array can be on the same or separate substrates in the modular housing. In another preferred embodiment, an integrated circuit is provided comprising a substrate, a cache memory array in the substrate, and a three-dimensional primary memory array above the substrate. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.