Memory with row redundancy
US6711056B2 · kind B2 · utility
22Cited by
15References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jul 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided. The memory device has a memory array and control circuitry to control operations to the memory array. A redundant register having a bit is also included. The bit is at a first level when two rows of the memory array are shorted together or at a second level when four rows of the memory array are shorted together. The control circuitry instructs an address counter, during an erase operation, to increment row addresses of the rows of the memory array by two rows when the bit is at the first level or four rows when the bit is at the second level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.