Patent · US Expired

1 T flash memory recovery scheme for over-erasure

US6711065B2 · kind B2 · utility

1Cited by

8References

12Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Danny Pak-Chum Shum · Poughkeepsie, US
George Tempel · Wriezen, DE
Christoph Ludwig · Radeberg, DE

Key dates

Filing date	Mar 28, 2002
Grant date	Mar 23, 2004
Priority date	—
Expiry date	Mar 28, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/3404
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Flash EEPROM cells are erased and recovered to a common threshold voltage by a two step process. First, the cells are erased. Second, the fixed (control) gates are set at a voltage of the same polarity as the programming voltage and at a magnitude of about half the programming voltage. The source is allowed to float and the drain (bitline) and body are set at a low level and at a polarity opposite to the programming voltage polarity.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.