Indication of the system operation frequency to a DRAM during power-up
US6711091B1 · kind B1 · utility
5Cited by
22References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Sep 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of using a memory chip includes operating a memory chip of a memory system and sending a command signal to the memory chip, wherein the command signal contains information regarding an operational frequency of a system clock signal of the memory system. The method provides the advantage of enabling high operation frequencies and thus increasing the SDRAM internal timing margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.