Split delay transmission line
US6711640B1 · kind B1 · utility
5Cited by
4References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2001 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | May 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10159
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A computer motherboard is described. That motherboard includes a memory controller and a memory section. A first trace couples the memory controller to the memory section, and a second trace couples the memory controller to the memory section. The first trace is joined with the second trace at the memory controller, the second trace is routed in parallel with the first trace, and the second trace is longer than the first trace. Also described is a computer system that includes this motherboard and a memory card.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.