Write and erase protection in a synchronous memory
US6711701B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | May 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous flash memory includes an array of non-volatile memory cells, and has a package configuration that is compatible with an SDRAM. The memory device includes a memory array, a programmable register circuitry to store protection data, and a voltage detector to determine if a memory power supply voltage drops below a predetermined level. Control circuitry is provided to program the register circuitry and prevent erase or write operations to the memory array in response to the voltage detector. In operation, the memory monitors a power supply voltage coupled to the memory, and prohibits write or erase operations from being performed if the supply voltage drops below a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.