Method of forming a semiconductor device with a capacitor including a polycrystalline tantalum oxide film dielectric
US6713343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2003 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Mar 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.