Method for fabricating a split gate flash memory cell
US6713349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2003 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | May 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method for fabricating a split gate flash memory cell. First, a substrate having a doped region covered by a first conductive layer is provided. A floating gate and a first insulating layer are successively formed over the substrate on both sides of the first conductive layer. Thereafter, a conformable second insulating layer and a conformable second conductive layer are successively formed on the substrate and the first insulating layer, and then a third insulating layer is formed thereon. The third insulating layer and the second conductive layer are successively etched back to expose the second insulating layer. The third insulating layer is removed using a cap layer formed on the second conductive layer as a mask to form an opening. Finally, the second conductive layer under the opening is removed to form a control gate underlying the cap layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.