Method to reduce parasitic capacitance of MOS transistors
US6713357B1 · kind B1 · utility
37Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2001 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | May 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced by use of sidewall spacers having an optimized cross-sectional shape, in conjunction with an overlying insulator layer comprised of a low-k dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.