Inventor · Cedar Park, TX, US

Mark W. Michael

115Patents

28h-index

37Co-inventors

90Inventor score

Filing activity: Mar 14, 1985 → Nov 28, 2011

Most-cited inventions

Patent	Title	Area	Cited by	Status
US6111260A	Method and apparatus for in situ anneal during ion implant	Electricity	279	Expired
US5850105A	Substantially planar semiconductor topography using dielectrics and chemical mechanical polish	Electricity	261	Expired
US5953626A	Dissolvable dielectric method	Electricity	110	Expired
US5918129A	Method of channel doping using diffusion from implanted polysilicon	Electricity	105	Expired
US6060345A	Method of making NMOS and PMOS devices with reduced masking steps	Electricity	104	Expired
US5759913A	Method of formation of an air gap within a semiconductor dielectric by solvent desorption	Electricity	99	Expired
US5827776A	Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines	Electricity	79	Expired
US5885877A	Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric	Electricity	69	Expired
US5930642A	Transistor with buried insulative layer beneath the channel region	Electricity	68	Expired
US5899732A	Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device	Electricity	67	Expired
US5792706A	Interlevel dielectric with air gaps to reduce permitivity	Electricity	63	Expired
US5963803A	Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths	Electricity	61	Expired
US5710054A	Method of forming a shallow junction by diffusion from a silicon-based spacer	Electricity	59	Expired
US5783864A	Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect	Electricity	55	Expired
US6225151A	Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion	Electricity	51	Expired
US5899727A	Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization	Electricity	45	Expired
US5888675A	Reticle that compensates for radiation-induced lens error in a photolithographic system	Physics	43	Expired
US6259142A	Multiple split gate semiconductor device and fabrication method	Electricity	41	Expired
US5840451A	Individually controllable radiation sources for providing an image pattern in a photolithographic system	Emerging Cross-Sectional Technologies	39	Expired
US5814555A	Interlevel dielectric with air gaps to lessen capacitive coupling	Electricity	38	Expired
US5998293A	Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect	Electricity	37	Expired
US6713357B1	Method to reduce parasitic capacitance of MOS transistors	Electricity	37	Expired
US5926713A	Method for achieving global planarization by forming minimum mesas in large field areas	Electricity	36	Expired
US6080629A	Ion implantation into a gate electrode layer using an implant profile displacement layer	Electricity	34	Expired
US6208015A	Interlevel dielectric with air gaps to lessen capacitive coupling	Electricity	33	Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.