SOI MOSFET having amorphized source drain and method of fabrication
US6713819B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Apr 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.