Low profile stacked multi-chip semiconductor package with chip carrier having opening and fabrication method of the semiconductor package
US6713857B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Dec 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked multi-chip semiconductor package and a fabrication method thereof are provided. A chip carrier is formed with an opening for receiving a first chip therein, and a second chip is stacked on the first chip and over the opening, wherein the first and second chips are respectively electrically connected to the chip carrier by bonding wires. A first encapsulant is formed to encapsulate first chip and corresponding bonding wires, and a second encapsulant is formed around the second chip to encompass a cavity for receiving the second chip and corresponding bonding wires therein. A lid is attached to the second encapsulant for covering the cavity. This semiconductor package allows high integration and increase in operational performances by virtue of stacked multi-chip structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.