Parallel channel programming scheme for MLC flash memory
US6714457B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Sep 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the present invention programming a plurality of MLC flash memory cells is done in parallel using a channel programming operation by applying a high positive voltage to a word line and positive voltages to the bit lines connected to cells to be programmed. The positive bit line voltages combined with the word line voltage create a channel voltage that is sufficient to program a required Vt level into each cell in parallel during a predetermined amount of time. Using a high positive word line voltage turns on the channel of a cell being programmed and eliminates potential breakdown condition, band to band tunneling current, channel pinch through and hole injection into the gate insulator, while allowing a small symmetrical cell that has low power consumption and a higher endurance cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.