Selective photoresist hardening to facilitate lateral trimming
US6716571B2 · kind B2 · utility
515Cited by
33References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2001 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Jun 20, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S430/143
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch rates in the vertical and horizontal directions. The modified photoresist layer is trimmed with a plasma etch. A feature included in the trimmed photoresist layer has a sub-lithographic lateral dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.