Semiconductor memory device with latch circuit and two magneto-resistance elements
US6717844B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 31, 2002 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Dec 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell in a MRAM includes four N channel MOS transistors responsive to a write permit signal attaining an H level to connect program lines of first and second tunneling magneto-resistance elements between first and second storage nodes and a line of ground potential to write signals in the first and second storage nodes to the first and second tunneling magneto-resistance elements. The writing of signals to first and second tunneling magneto-resistance elements can be performed more rapidly than the conventional case where signals in the first and second storage nodes are read out, and then written into the tunneling magneto-resistance elements via a write circuit and a write bit line pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.