Method of manufacturing semiconductor device
US6720222B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2002 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Oct 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 for defining side walls is subsequently formed on the whole surface of the substrate 100 in a greater thickness of approximately 2000 angstrom than a standard thickness. Over-etching of the sixth oxide film 119 defines side walls 119SW. Non-required portions of the oxide film 112 are then etched off with a resist R15A. This causes a drain-source forming region, which is expected to form a drain area and a source area, to be open in an element forming region in a high-breakdown-voltage nMOS area HVn. The resist R15A is not removed but is used continuously, and an n-type impurity ion is implanted into the open drain-source forming region. This arrangement enables both a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor to be formed efficiently on an identical substrate without damaging the characteristics of the respective MOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.