Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices
US6720619B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2002 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Dec 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
Abstract
The present disclosure provides a system and method for forming device on an insulator material. First, a semiconductor depletion material is formed with a predetermined height and width overlying a predetermined portion of the substrate to from an active region. An isolation material formed on top of the substrate surrounding the active region so as to bury a bottom portion of the active region therein, thereby exposing a top portion of the active region. A gate dielectric layer is deposited for covering the exposed the top and two sidewalls of the top portion of the active region, and at least one gate electrode is then formed on top of the gate dielectric layer and extending through two sidewalls thereof to reach the isolation material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.