Transistor having a deposited dual-layer spacer structure

US6720631B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Lawrence N. Brigham · Beaverton, US
• Raymond E. Cotner · Beaverton, US
• Makarem A. Hussein · Beaverton, US

Key dates

• Filing date: Oct 20, 1997
• Grant date: Apr 13, 2004
• Expiry date: Oct 20, 2017

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

A transistor comprising a deposited dual-layer spacer structure and method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.