Semiconductor memory device
US6721223B2 · kind B2 · utility
81Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2002 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | May 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data specifying details of refresh to be executed in the self-refresh mode is stored in a register circuit in a mode register. A refresh period and refresh region are determined according to data stored in register circuit and a refresh control circuit generates a control signal and a refresh address that are required for refresh. Stored data can be stably held in the self-refresh mode in which data holding is performed with reduced current consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.