Patent · US Expired

System for testing fast integrated digital circuits, in particular semiconductor memory modules

US6721904B2 · kind B2 · utility

9Cited by

5References

29Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Wolfgang Ernst · Munich, DE
Gunnar Krause · Munich, DE
Justus Kuhn · Birkenfeld, DE
Jens Lüpke · Hersbruck, DE
Jochen Müller · Hersbruck, DE
Peter Pöchmüller · Birkenfeld, DE
Michael Schittenhelm · Poing, DE

Key dates

Filing date	Jul 18, 2001
Grant date	Apr 13, 2004
Priority date	—
Expiry date	Sep 13, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/56012
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.