Semiconductor device used in two systems having different power supply voltages
US6724223B2 · kind B2 · utility
13Cited by
3References
16Claims
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Key dates
| Filing date | Nov 5, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Nov 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.