Integrated memory having a precharge circuit for precharging a bit line
US6724672B2 · kind B2 · utility
8Cited by
4References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Dec 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory having a memory cell array: including word lines for selecting memory cells, bit lines for reading out or writing data signals of the memory cells, a precharge circuit for precharging at least one of the bit lines to a precharge voltage that differs from a supply voltage of the memory. The precharge circuit has a loop regulating circuit for setting the precharge voltage using an actual voltage of the one of the bit lines. The precharge circuit makes it possible to reduce the power loss of the memory in conjunction with low area consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.