Semiconductor memory device allowing high density structure or high performance
US6724679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Apr 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.